EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Design-Reuse

Siemens launches Tessent tool for Verilog and RTL design for test

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...
Design-Reuse

Bluespec Updates ESL Synthesis Toolset; Offers Improved Verilog RTL Output for Practical IP Delivery Vehicle

WALTHAM, Mass.--May 11, 2006--Bluespec Inc. today released the latest version of its electronic system level (ESL) Synthesis software, offering a practical delivery vehicle for intellectual property ...
Semiconductor Engineering

Get To Know The Gate-Level Power Aware Simulation

The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from ...
Electronic Design

Compiler Turns ANSI C Into Verilog

The C2R Compiler enables full-chip designs to be architected, verified, and implemented using ANSI C as the design language in a flow that is two to three times faster than using the traditional ...
Hackaday

Xilinx FPGAs In C For Free

When you think of developing with FPGAs, you usually think of writing Verilog or VHDL. However, there’s been a relatively recent trend to use C to describe what an FPGA should do and have tools that ...