EDN

Part 2 of Cooley survey shows SystemC use declinging; SystemVerilog increasing

Hey folks, John Cooley’s posted on deepchip.com Part 2 of his IC verification census, which features data indicating that SystemC use is decreasing while SystemVerilog use is increasing and that ...
EDN

The war is over: C++ and SystemC coexist in a single flow

Since its debut in 2004, the current generation of high-level synthesis (HLS) tools has made tremendous progress in terms of both quality of results (QoR) and wider applicability. The success of this ...
Semiconductor Engineering

Using SystemC TLM Modeling To Solve AI Data Movement Challenges

In AI silicon, the performance numbers tell only part of the story. Marketing claims often highlight headline metrics such as trillions of operations per second, tensor throughput, matrix dimensions, ...
Semiconductor Engineering

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...