Design-Reuse

ARM And Synopsys to Deliver Industry’s First Reference Verification Methodology Based on SystemVerilog

Companies to Publish “SystemVerilog Verification Methodology Manual,†a “How-To†Book on Verification Using SystemVerilog CAMBRIDGE, UK AND MOUNTAIN VIEW, Calif. – February 16, 2004 - ARM ...
Design-Reuse

Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP

CAMPBELL, Calif. -- November 3, 2008--Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, under their IP Development Program - ...
Electronic Design

ARM, Synopsys Partner For SystemVerilog Verification

A reference methodology to define a coverage-driven verification architecture using SystemVerilog is in the works from ARM and Synopsys. The companies will publish the methodology in the co-authored ...
EDN

Synopsys Delivers Next-Generation Verification IP for Micron’s Hybrid Memory Cube Architecture

Synopsys VC VIP for HMC uses a next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments to ...
Electronic Design

Step-By-Step Functional Verification With SystemVerilog And OVM

The industry’s first book covering the Open Verification Methodology (OVM), titled “Step-by-Step Functional Verification with SystemVerilog and OVM,” provides a complete reference to adopting the OVM ...
New Electronics

Open-source SystemVerilog RISC-V processor functional coverage library

Imperas Software has announced the release of the first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores. The initial release is for RV32IMC, RV64 and other ...