Business Wire

Silicon Valley Startup Granted US Patent on Critical DDR2/DDR3 Timing Innovation for Chip Designs

SANTA CLARA, Calif.--(BUSINESS WIRE)--Uniquify, a Silicon Valley semiconductor IP start-up (http://www.uniquify.com), today announced that it has been granted a ...
EDN

DS75 2-Wire Communication SDA Hold Time Clarification

This application note details the difference between DS75 communication timing and the I²C specification. Under I²C, the SCL and SDA lines are allowed to transition simultaneously because SDA is ...
Design-Reuse

I2C Interface Timing Specifications and Constraints

I2C is a two-wire, bidirectional bus protocol that enables effective communication between one master (or multiple masters) and one or more slave devices. It is a straightforward, half-Duplex, ...
Electronic Design

Interview: Josh Lee Addresses DDR And Self Calibrating Logic

Josh Lee is president and CEO of Uniquify. Uniquify has developed IP for building high performance DDR subsystems. The systems are designed to deliver better performance, lower power and smaller area, ...
Hackaday

I2C Tap Helps Assign Blame For SDA Conflicts

If you’ve ever debugged a misbehaving I2C circuit, you probably know how frustrating it can be. Thankfully [Jim] over at Hackaday.io, has a proto-boardable circuit that can help! Inter-integrated ...