The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...

The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...

RISC-V International Association is developing a number of optional extensions intended to support specific industries as well as the overall computing industry in new and unprecedented ways. Three ...

SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive Inc., the founder and leader of RISC-V computing, today announced the release of the latest version of its SiFive® Intelligence™ X280 processor, which ...

Benchmarking tool Geekbench has been updated to version 6.4, seeing added support for RISC-V Vector Extensions and Arm Scalable Matrix Extensions. Geekbench is a highly-used benchmark tool, providing ...

San Jose, CA, Nov. 06, 2020 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding Premier member ...

Though the RISC-V Summit North America is over, you can peruse the videos of most of the keynotes and sessions here. The list is quite long, so we picked a few and included them in this space, such as ...

Andes Technology Corporation (TWSE: 6533), a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier Member of RISC-V International, today announced a ...

A new technical paper titled “Test-driving RISC-V Vector hardware for HPC” was published by researchers at University of Edinburgh. “Whilst the RISC-V Vector extension (RVV) has been ratified, at the ...

SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste ...