J-LINK REDUCES JTAG DEBUG PINCOUNT FROM 5 to 1! Pittsford, New York—Traditional JTAG boundary-scan testing normally takes up 5 valuable pins on an i.c., requires 5 resistors, and increases chip power.

SANTA CRUZ, Calif. — Claiming to dramatically speed test vector debug time for users of Synopsys' design for test (DFT) products, Intellitech Corp. has announced the Nebula silicon debugger. It claims ...

TurboDebug-SOC/Memory locates and diagnoses faults in embedded SOC memories, User-friendly software runs on a PC, Annotates debug results on PC display NEW ORLEANS--(BUSINESS WIRE)--June 10, 2002-- ...

CAMBRIDGE, UK – Sept 23, 2009 – ARM [(LSE: ARM); (Nasdaq: ARMH)] has introduced multi-drop support into the ARM® CoreSight™ Serial Wire Debug (SWD) solution, enabling simultaneous connection to ...

WILSONVILLE, Ore.--(BUSINESS WIRE)-- Mentor Graphics Corporation (NAS: MENT) today announced its new Tessent® IJTAG solution, which allows designers to easily reuse test, monitoring and debugging ...

Tap-Hat is a multi-purpose JTAG debugger board for those developing software to run on Raspberry Pi: RTOSs, Linux and bare-metal code in particular. Photo of prototype As well as this, the board can ...

In an effort to further improve the Open Core Protocol’s (OCP’s) ability to speed IP integration, the OCP International Partnership has opened its new debug specification to member review. In an ...

Vector and Lauterbach are offering an integrated solution for ECU software development based on the new ASAM standard “Software Debugging over XCP”. It is designed to eliminate the need to repeatedly ...

You can use Linux and still employ a methodology that includes all of the different phases of the ever-critical debugging process. A growing number of embedded developers are experimenting with the ...