The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

New manufacturing test challenges are raised with SoC technology advances where both test quality and test costs are affected with a direct impact on current Design-For-Test (DFT) methodologies and ...

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...

This is accomplished by connecting all of the design's registers in serial fashion, allowing test engineers to shift data in and out through a few ports at the chip level (Fig. 1). That allows, for ...

Connected devices and systems have become an integral part of our everyday life and we take this for granted. Finding the fastest way to our destination with a smartphone, reading the news on a tablet ...