Design-Reuse

An FPGA primer for ASIC designers

With the advent of new technologies in IC design and complexity of the business models, chip designers may want to explore different choices available to them for implementation. ASICs have been the ...
Design-Reuse

Magma and ChipX Extend Integrated RTL-to-GDSII Design Flow to Next-Generation Structured ASIC Designs

Magma Blast Create SA, Blast Fusion SA and ChipX CX6000 Structured ASIC combine to reduce cost and cycle time of high-performance designs SANTA CLARA, Calif., Nov. 9, 2005 - ChipX, the structured ASIC ...
EDN

HDL-design challenges and philosophies for real-world ASIC implementations

New requirements for the MAC (medium-access control) and PHY (physical-layer interface) of a wireless-communications system can pose significant challenges for system designers looking to quickly get ...
Electronic Design

Hybrid ASIC Chisels Down SoC Development Costs

Configuring a structured ASIC as IP on a standard-cell device, the company's Hybrid ASIC forecasts rapid and economical system-on-chip (SoC0 development with significant savings in non-recurring ...
EDN

What platform ASICs are and when to use them

Although system designers in need of custom logic solutions are increasingly faced with new technical challenges, they are armed with new advancements and choices in custom silicon offerings. One of ...
CoinTelegraph

Ethereum Devs Delay ASIC-Resistant PoW Algorithm Decision Until Third-Party Audit

Ethereum (ETH) core developers have delayed the decision to implement Application-Specific Integrated Circuit (ASIC)-resistant proof-of-work (PoW) algorithm ProgPoW. According to an Ethereum core ...